Tag: journalism

MRAM Momentum Poised to Disrupt Memory Workhorses [Byline]

/ Gary Hilson

TORONTO — Last year could be described as a tipping point for the magneto-resistive random access memory (MRAM) market. Up until then, Everspin Technologies was the only company shipping commercial MRAM products. But as Spin Transfer Technologies (STT) CEO Barry Hoberman is always quick to acknowledge, Everspin’s success has helped to pave the way for other MRAM players.

The genesis of STT goes back as far as 2001 with technology originally developed from research conducted by New York University Professor Andrew Kent. STT was formed and incubated by Boston-based Allied Minds in 2007. In September 2016, the developer of orthogonal spin transfer MRAM technology (OST-MRAM) announced it had fabricated perpendicular MRAM magnetic tunnel junctions (MTJs) as small as 20nm at its development fab based at the company’s headquarters in Fremont, Calif.

Since then, STT has delivered samples of its spin transfer torque MRAM to customers in North America and Asia, a milestone that’s significant in that it’s one of several emerging memories considered to be a next-generation candidate to replace DRAM and NAND flash, which face scaling challenges as the industry moves to smaller nodes. STT is one of a handful of firms developing MRAM, so the delivery of samples is an important proof point validating both MRAM in general, and STT’s technology in particular.

EE Times recently spoke with Hoberman about the company’s ramp up, and the opportunities for MRAM as more players go to market, including where it might be a viable replacement for incumbent technologies.

Read the full Q&A on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Faster Networks Push Interface Development [Byline]

/ Gary Hilson

TORONTO – As Ethernet speeds get faster, Rambus is looking to make sure memory and interfaces can keep up with the recent launch 56G SerDes PHY.

The analog-to-digital converter (ADC) and (DSP) architecture of the 56G SerDes PHY is designed meet the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications, said Mohit Gupta, senior director of product marketing at Rambus. This means it can support scaling to speeds as fast as 112G, which are required in the networking and enterprise segments, such as enterprise server racks that are moving from 100G to 400G.

“Ethernet is moving faster than ever,” Gupta said. “The pace has picked up substantially due to big data, the Internet of Things (IoT) and other trends putting high demands on communication channels. There is already a forum for 112G SerDes speed which will drive the 800G standard.”

One clear usage case, said Gupta, is data center deployment by the “big four” — Facebook, Microsoft, Amazon and Google.

Read my full article on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Research suggests cities with hosted data centres draw more cybercriminal activity [Portfolio]

/ Gary Hilson

ThreatMetrix Top Cities GraphicHosted data centers have become a common avenue for enterprises to access and deliver IT services, but they’re also a hit with cyber criminals.

According to a recent report by ThreatMatrix, there is a correlation between top U.S. cities for online fraud and those that are home to hosted data centers, with Tampa, Fla. topping the list, followed by New York. Major U.S. cities rounding out the top 10 included Los Angeles, Atlanta and Chicago. [Read the full story on IT World Canada]

EE Times: PCIe Storage Spec Group Incorporates for Added Clout [Portfolio]

/ Gary Hilson

EE TimesThe NVM Express Work Group has decided to incorporate itself to further the NVM Express (NVMe) specification for accessing solid-state disks (SSDs) on a PCI Express (PCIe) bus. NVMe is a standardized register interface, command, and feature set for PCIe-based storage technologies such as SSDs, designed specifically for non-volatile memory. It is optimized for high performance and low latency, scaling from client to enterprise segments. Read Full Article.

EE Times: Samsung Pushes DDR3 Design & Manufacturing to New Efficiencies [Portfolio]

/ Gary Hilson

EE TimesAs DDR4 awaits widespread adoption and new technologies such as hybrid memory cube continue to be fleshed out, there remains opportunity to improve on DDR3’s performance, and more importantly, its design and manufacturing. Last week, Samsung announced it was mass producing what the company said is the most advanced 4Gb DDR3 memory based on a new 20 nanometer process technology using immersion ArF lithography. Read Full Article.

EE Times: Research Labs Push the Bleeding Edge of Shared Memory Systems [Portfolio]

/ Gary Hilson

EE TimesWhile businesses turn to proven systems for their high-performance computing needs, research institutions are more willing to experiment and take a chance on the latest and greatest to solve complex problems. The Japan Agency for Marine-Earth Science and Technology (JAMSTEC) is the perfect example: It recently selected SGI’s large-scale shared memory system, the UV 2000, for installation at its Earth Simulator supercomputer center. Read Full Article.

EE Times: DDR4 Heir-Apparent Makes Progress [Portfolio]

/ Gary Hilson

EE TimesThe Hybrid Memory Cube Consortium (HMCC) is making steady progress on bringing one of the most discussed heirs to DDR4 closer to reality by releasing an update to the HMC specification late last month. The first draft of the second-generation specification supports increased data rates that advance short-reach (SR) performance from 10 Gbit/s, 12.5 Gbit/s, and 15 Gbit/s, up to 30 Gbit/s. Read Full Article.

RONNIEE Card Shares Memory Across Networks [Portfolio]

/ Gary Hilson

EE TimesStartup A3Cube recently announced a new network interface card, dubbed RONNIEE Express, designed to eliminate the I/O performance gap between CPU power and data access performance for datacenters, big data, and high-performance computing applications. The company said that by turning PCI Express into an intelligent network fabric, it can exceed existing networking technologies such as Ethernet, InfiniBand, and Fibre Channel, and improve memory latencies. Read my full story on EE Times.

EE Times Roundup: Next Generation Memory [Portfolio]

/ Gary Hilson

EE TimesThere are a number of next generation memory technologies on the horizon that hold great promise to meet the evolving needs of consumer devices and enterprise storage systems and applications. Some have been in development for a number of years, and are close to a critical turning point that will see them widely adopted. Here’s a few that merit watching in the next year, including several DRAM alternatives. Read my full article on EE Times.