Tag: ee times

Intel’s 3D XPoint Plans Clearer Than Micron’s [Byline]

/ Gary Hilson

TORONTO — What the future holds for 3D XPoint — now that Intel and Micron have announced plans to end their joint development program — depends on who you talk to.

Or who you don’t talk to. Micron, for its part, isn’t offering any more guidance right now beyond what was stated in a joint news release issued earlier this week. “The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019,” the statement reads. “Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.”

Intel is still bullish on the technology. In a telephone interview with EE Times, Bill Leszinske, vice president of Intel’s non-volatile memory solutions group, said it makes sense for Intel to continue on its present path.

Read my full EE Times story

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

NOR Flash is Road Tested [Byline]

/ Gary Hilson

TORONTO — As cars get smarter and demand more memory, many technologies are angling for the driver’s seat, but it’s safe to say NOR flash at least gets to ride shotgun.

As a successor to EEPROM in many applications thanks to its programmability capabilities, NOR flash is finding new opportunities in application areas that need fast, non-volatile memory, including communications, industrial and automotive. The latter, of course, is getting a lot of attention thanks to autonomous vehicle development.

Macronix International, which describes itself as the leading supplier of NOR flash overall, find itself in the third position for automotive. But Anthony Le, senior director of marketing, ecosystem partnership and North America automotive, said the company is confident it will lead that segment in the next two to three years.

Read the full story on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Micron Talks 3D NAND Sans Intel [Byline]

/ Gary Hilson

TORONTO — On the heels of shaking up its partnership with Intel, Micron Technology Chief Technology Officer Ernie Maddock took the stage at the J.P. Morgan 16th Annual Tech Forum at the 2018 International CES to field questions about the road ahead.

In a Q&A and session moderated by Harlan Sur, analyst for U.S. Semiconductor and Semiconductor Capital Equipment Research at J.P. Morgan, Maddock emphasized that the update to Micron’s working relationship with Intel is only related to NAND development.

At the top of the week, the companies announced they have mutually agreed to work independently on future generations of 3D NAND. Micron and Intel will complete development of their third-gen 3D NAND technology toward the end of the year and into 2019. Maddock said based on evolving roadmaps and the needs of each company’s respective markets, it made sense to diverge for the next node.

Read the full article over at EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

NVM Express Set for Busy 2018 [Portfolio]

/ Gary Hilson

TORONTO — Following on the heels of a major specification update and its eighth annual plug fest, NVM Express is poised to have a busy year as it continues to develop the base NVMe specification while expanding the NVMe Management Interface (NVMe-MI) specification and one for accessing SSDs on a PCIe bus over fabrics.

In June, the NVMe specification got its first major update in nearly three years, putting it on the cusp of becoming the defacto standard for SSD interfaces. Version 1.3 added a significant number of new features, something that hasn’t been done since November 2014, encompassing 24 technical proposals spread across three major buckets that address client, enterprise and cloud features. Most significant was improved support for virtualization so developers can more flexibly assign SSD resources to specific virtual machines, thereby addressing latency.

Meanwhile, the eighth NVMe Plugfest at the University of New Hampshire Interoperability Laboratory last fall offered the first official NVMe Over Fabrics (NVMe-oF) compliance and interoperability transport layer testing for RoCE, Remote Direct Memory Access (RDMA) over Converged Ethernet, and the Fibre Channel. UNH-IOL fills the role of independent testing provider of standards conformance solutions and multi-vendor interoperability, and the latest plugfest generated 14 new certified products for the base NVMe integrators list and one for the NVMe-MI integrators list. Eight inaugural products were also approved for the newly launched NVMe-oF integrators list, which accepts RoCE initiators and targets, Ethernet switches, as well as Fibre Channel initiator, targets and switches and software.

Read the full story over at EE Times.

IBM Simulates Complex Chemistry with Quantum Computing [Byline]

/ Gary Hilson

TORONTO — A novel algorithm developed by IBM scientists is improving the understanding of complex chemical reactions and optimizing quantum computing.

The scientists have developed a new approach to simulate molecules on a quantum computer using a seven-qubit quantum processor to address the molecular structure problem for beryllium hydride (BeH2), which is the largest molecule simulated on a quantum computer to date, according to IBM. The results are significant as they could lead to practical applications such as the creation of novel materials, development of personalized drugs and discovery of more efficient and sustainable energy sources.

In a telephone interview with EE Times, IBM quantum computer research team member Abhinav Kandala outlined how they implemented an algorithm that is efficient with respect to the number of quantum operations required for the simulation. Using six qubits of a seven-qubit processor, they were able to measure BeH2’s lowest energy state, a key measurement for understanding chemical reactions. The results were just published in the peer-reviewed journal Nature, which Kandala co-authored.

Read the full story on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

MRAM Momentum Poised to Disrupt Memory Workhorses [Byline]

/ Gary Hilson

TORONTO — Last year could be described as a tipping point for the magneto-resistive random access memory (MRAM) market. Up until then, Everspin Technologies was the only company shipping commercial MRAM products. But as Spin Transfer Technologies (STT) CEO Barry Hoberman is always quick to acknowledge, Everspin’s success has helped to pave the way for other MRAM players.

The genesis of STT goes back as far as 2001 with technology originally developed from research conducted by New York University Professor Andrew Kent. STT was formed and incubated by Boston-based Allied Minds in 2007. In September 2016, the developer of orthogonal spin transfer MRAM technology (OST-MRAM) announced it had fabricated perpendicular MRAM magnetic tunnel junctions (MTJs) as small as 20nm at its development fab based at the company’s headquarters in Fremont, Calif.

Since then, STT has delivered samples of its spin transfer torque MRAM to customers in North America and Asia, a milestone that’s significant in that it’s one of several emerging memories considered to be a next-generation candidate to replace DRAM and NAND flash, which face scaling challenges as the industry moves to smaller nodes. STT is one of a handful of firms developing MRAM, so the delivery of samples is an important proof point validating both MRAM in general, and STT’s technology in particular.

EE Times recently spoke with Hoberman about the company’s ramp up, and the opportunities for MRAM as more players go to market, including where it might be a viable replacement for incumbent technologies.

Read the full Q&A on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Faster Networks Push Interface Development [Byline]

/ Gary Hilson

TORONTO – As Ethernet speeds get faster, Rambus is looking to make sure memory and interfaces can keep up with the recent launch 56G SerDes PHY.

The analog-to-digital converter (ADC) and (DSP) architecture of the 56G SerDes PHY is designed meet the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications, said Mohit Gupta, senior director of product marketing at Rambus. This means it can support scaling to speeds as fast as 112G, which are required in the networking and enterprise segments, such as enterprise server racks that are moving from 100G to 400G.

“Ethernet is moving faster than ever,” Gupta said. “The pace has picked up substantially due to big data, the Internet of Things (IoT) and other trends putting high demands on communication channels. There is already a forum for 112G SerDes speed which will drive the 800G standard.”

One clear usage case, said Gupta, is data center deployment by the “big four” — Facebook, Microsoft, Amazon and Google.

Read my full article on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Micron CEO Durcan to Retire [Byline]

/ Gary Hilson

Micron Technology Inc. CEO Mark Durcan announced his pending retirement Thursday (Feb. 2). No timeframe has been set for Durcan’s retirement, but he will continue to head the company as CEO for the time being.

Micron (Boise, Idaho) said its board of directors has formed a special committee to oversee the succession process and has initiated a search, with the assistance of an executive search firm, to identify and vet candidates. Durcan has pledged to help with the search process and the transition. Read my full article on EE Times.

Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Persistent Memory Platform Support Will Take Time [Portfolio]

/ Gary Hilson

TORONTO — Over the last several years, there’s been an increasing overlap between what was traditionally seen as memory and traditionally seen as storage, as well as the increasing use of persistent memory.

Last week’s Persistent Memory Summit in San Jose, organized by the Storage Networking Industry Association (SNIA) as part of its Solid State Storage Initiative (SSSI), included a presentation by Steve Pawlowski, vice president of advance computing solutions at Micron, outlining how computing architectures must change to get the right data to the processor efficiently and how persistent memory such as NVDIMMs can play a role.

EE Times spoke to Pawlowski following his SNIA keynote on why new computing architectures must support current software applications, the current roadmap for NV-DIMMs, and what might be the non-volatile memory of choice down the road.

Read my full Q+A on EE Times.

Miniaturization, IoT Fuel Electronics Adhesive Growth [Portfolio]

/ Gary Hilson

TORONTO — The market for high-quality electronics is growing, and with that also comes a rising need for technology adhesives. This demand has been driven, in part, by miniaturization.

“As the market for high-quality electronics has increased in the past few years, the need for material to protect and bond electronic components has also increased,” said Technavio Senior Industry Analyst Chandrakumar Badala Jaganathan, in an interview with EE Times.

The research firm’s recent Global Electronic Adhesives Market 2017–2021 report is forecasting the market to grow at a compound annual growth rate (CAGR) of close to 10% between now and 2021, said Jaganathan. “The market in 2017 is expected to grow by 8.89% compared to 2016.”

Read my full article on EE Times.