Researchers in Canada’s national capital have devised a smart approach to optimize the effectiveness of solar panels by enhancing them with artificial ground reflectors.

The University of Ottawa’s SUNLAB collaborated with the National Renewable Energy Laboratory (NREL) in Golden, Colorado, to study how reflective ground covers affect solar energy output.

The research found that placing reflective surfaces under solar panels can increase their energy output by up to 4.5%. It involved pairing high ground reflectivity with bifacial solar modules, paired with high ground reflectivity.

Solar power can be some of the cheapest power in the world, especially in sun drenched regions, such as Saudi Arabia or Quatar. But other countries like the United States and Canada have different weather patterns.

The research findings are particularly significant in Canada, where snow cover persists for three to four months of the year in major cities like Ottawa and Toronto, and 65% of the country’s vast landmass experiences snow cover for over half the year. Additionally, given that approximately 4% of the world’s land areas are classified as sandy deserts, this finding has global applications.

The efficiency of most solar panels ranges from 20% to 25%, and panel materials have evolved in the last five to 10 years from aluminum back surface field to passivated emitter and rear contact (PERC), which is much more efficient with only minor changes to the manufacturing process.

PERC cells can be made bifacial more easily, which has facilitated the production of bifacial modules globally.

The SUNLAB study at NREL site looked at the effect of high albedo (70% reflective) artificial reflectors on single-axis-tracked bifacial photovoltaic systems through ray-trace modeling and field measurements. The researchers tested a range of reflector configurations by varying reflector size and placement and demonstrated that reflectors increased daily energy yield up to 6.2% relative to natural albedo for PERC modules.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Recent advances in artificial intelligence may appear revolutionary, but JEDEC is keeping an evolutionary approach for Graphics Double Data Rate (GDDR) standards, even as it’s being increasingly used for AI applications.

The JEDEC Solid State Technology Association’s GDDR7 standard continues the generation-to-generation tradition of double the bandwidth and double the capacity while keeping a lid on power consumption.

The latest iteration of GDDR offers twice the bandwidth of its predecessor, reaching up to 192 GB/s per device. GDDR7 doubles the number of independent channels, from two in GDDR6 to four.

It’s also the first JEDEC standard DRAM to use the pulse-amplitude modulation (PAM) interface for high-frequency operations. Using a PAM3 interface improves the signal-to-noise ratio for high-frequency operation while enhancing energy efficiency. PAM3 also offers a higher data transmission rate per cycle, resulting in improved performance versus the traditional non-return-to-zero (NRZ) interface.

GDDR7 addresses the industry’s need for reliability, availability and serviceability (RAS) by incorporating the latest data integrity features, including on-die error-correction coding with real-time reporting, data poison, Error check and Scrub, and command address parity with command blocking (CAPARBLK).

With companies like Micron Technology selling out of HBM3, GDDR can be a viable alternative for some AI workloads, and AI demands are shaping the evolution of GDDR. One of the reasons GDDR has found uses beyond its initial target market is its ability to do matrix algebra, which helps GPUs handle AI workloads and computer-generated special effects.

GPU maker Nvidia wanted a faster, more reliable memory—hence, the adoption of PAM, as transmitting data at super-fast rates means channel integrity becomes a bigger concern.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

As the edge gets smarter, the challenge becomes increasing machine learning (ML) and inference without spiking power consumption—microcontrollers (MCUs) optimized for edge AI applications are important pieces of the puzzle.

Infineon Technologies’ PSOC Edge MCU series is aimed at developers looking to bring new ML-enabled internet of things, consumer and industrial applications to market. The E81, E83 and E84 options focus on usability.

The PSOC MCU series has an Arm Cortex-M55 architecture, which is augmented with Helium DSP support alongside Arm Ethos-U55 and Cortex-M33. All of this is integrated with Infineon’s proprietary hardware accelerator, NNLite, which is designed for neural network acceleration.

At the high end of the series, the E84 is aimed at graphics-enabled applications, such as fitness wearables, high-end smart thermostats or smart locks, allowing more ML to be done on-chip. Many applications are sensor-based to support anomaly detection and predictive maintenance in industrial settings, as well as to detect people when they walk into the room for security or environmental control purposes.

Like Infineon, Ambiq is looking to make the edge smarter without consuming more power. It recently launched the Apollo510, the first in its Apollo5 SoC series, to support endpoint AI, including speech, vision, health and industrial AI models, on battery-powered devices.

Apollo510’s hardware and software use the Arm Cortex-M55 CPU with Arm Helium to reach processing speeds up to 250 MHz and achieve up to 10× better latency than its predecessor, the Apollo4. Like Infineon, Ambiq is eyeing energy efficiency to support sophisticated speech, vision, health and industrial AI models on battery-powered devices.

The introduction of new MCUs to support edge AI comes at a time when generative AI (GenAI) is getting most of the attention, despite representing a small percentage of AI that’s being deployed.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

The graying of the semiconductor workforce as onshore manufacturing ramps up means the days of chip companies poaching each other’s talent are numbered—their local communities must develop talent through the collaboration of schools and workforce development organizations.

In the first of two panel discussions hosted by the National Institute of Innovation and Technology (NIIT), those collaborating to help build the talent pipeline for Texas’s semiconductor and advanced manufacturing sectors said they are working to deliver flexible options for apprenticeships to meet the demand for skilled workers with options that allow apprentices to earn a living while learning.

Austin Community College District has been collaborating with workforce development organizations and semiconductor companies to create entry pathways at various points and equip students with the right skills, especially in manufacturing.

Austin Community College District is increasingly giving tours to middle school students to expose them early to programs that will set them on a career path in semiconductors and advanced manufacturing.

The college’s Make It Center provides guests of all ages a chance to experience a wide range of experiences to pique their interest in advanced manufacturing careers, including an area dubbed “The Forge,” where they can use 3D printing, laser cutters and vacuum formers to create career-related projects. There are also virtual-reality simulations that allow users to “try out” different careers by immersing themselves in various job sites.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Semiconductor technologies live and die by industry standards, but are there times when it makes sense to build a heavily customized—even proprietary—memory device?

The chip sector is replete with standards organizations that guide the evolution of widely adopted memory devices. JEDEC is responsible for DRAM, LPPDR, GDDR and high-bandwidth memory (HBM), among others. The Peripheral Component Interconnect Express Special Interest Group takes care of the most ubiquitous protocol for data movement, while NVMe Express and the CXL Consortium built their specifications with PCIe as their foundation. Most recently, the UCIe was developed to bring best practices to chiplets.

The highway of DRAM technologies is littered with the roadkill of non-JEDEC-standard memories. If something isn’t JEDEC-standard, or if a DRAM vendor tries to go it alone with something that they want to differentiate with, it’s going to die.

Among the many abandoned memories that never saw widespread use are Micron Technology’s HBM competitor, Hybrid Memory Cube, and Rambus’s virtual-channel DRAM, even though the latter had the backing of Intel.

The value of a standardized memory device is that it can be multi-sourced—an SK Hynix product will plug into the same socket as a Micron product.

That’s not to say some vendors aren’t offering special features. There will be DRAM vendors that will have their own special features that they unlock for special customers, and it’s still standard DRAM.

Some memories that are developed by more than one vendor may show potential but are subsequently abandoned by all but one of the vendors. Reduced-latency DRAM was initially developed by Infineon Technologies in the late 1990s; Micron was subsequently brought in as a development partner and a second source, but Infineon opted to exit the market.

The challenge of being the sole source of a memory product that has a strong customer base—especially if it’s a Tier 1 customer—is that it’s difficult to end-of-life the product.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.

Digital twins aren’t a new tool for the chip industry, but they are getting democratized to a point where they are more accessible for a broader set of commercial applications.

The ability to ingest more, higher-quality data from a wider array of sources and the application of artificial intelligence is helping to extend digital twins beyond product design to virtually envision manufacturing environments, which will reduce waste as well as contribute to meeting sustainability goals. And as the chip industry ramps up U.S. onshore manufacturing in the wake of the CHIPS Act, digital twins are poised to be a critical tool for workforce development while also accelerating productivity.

In early February 2024, the National Institute of Standards and Technology (NIST) announced its intent to create a new semiconductor manufacturing institute that will use digital twin technology for production, packaging and assembly. NIST is looking to corral curriculum and best practices through its CHIPS Research and Development Office to launch a competition for a new public-private Manufacturing USA Institute.

Digital twins are more effective when silos of information are eliminated, Grieves added. “Depending on what functional area they were in, you wound up with huge inefficiencies or the inability to optimize the entire process.”

Expanding the use of digital twins out to manufacturing facilities is the natural evolution of the virtual approach the chip industry has used for decades. Digital twins are being extended to visualize equipment and manufacturing facilities before they are built, then optimized once they are in production.

Digital twins can be used to build anything, so why not the manufacturing facilities that produce semiconductors—not just the devices themselves?

Building a digital twin of a fab allows for the modeling of the manufacturing of the chip, making it possible to optimize a facility before concrete is ever poured.
A digital twin does more than simulate the manufacturing process. It also optimizes all the electricity, water and chemicals being used, which helps to achieve sustainability goals.

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Gary Hilson is a freelance writer with a focus on B2B technology, including information technology, cybersecurity, and semiconductors.