TORONTO — On the heels of shaking up its partnership with Intel, Micron Technology Chief Technology Officer Ernie Maddock took the stage at the J.P. Morgan 16th Annual Tech Forum at the 2018 International CES to field questions about the road ahead.
In a Q&A and session moderated by Harlan Sur, analyst for U.S. Semiconductor and Semiconductor Capital Equipment Research at J.P. Morgan, Maddock emphasized that the update to Micron’s working relationship with Intel is only related to NAND development.
At the top of the week, the companies announced they have mutually agreed to work independently on future generations of 3D NAND. Micron and Intel will complete development of their third-gen 3D NAND technology toward the end of the year and into 2019. Maddock said based on evolving roadmaps and the needs of each company’s respective markets, it made sense to diverge for the next node.
Read the full article over at EE Times.
TORONTO — Following on the heels of a major specification update and its eighth annual plug fest, NVM Express is poised to have a busy year as it continues to develop the base NVMe specification while expanding the NVMe Management Interface (NVMe-MI) specification and one for accessing SSDs on a PCIe bus over fabrics.
In June, the NVMe specification got its first major update in nearly three years, putting it on the cusp of becoming the defacto standard for SSD interfaces. Version 1.3 added a significant number of new features, something that hasn’t been done since November 2014, encompassing 24 technical proposals spread across three major buckets that address client, enterprise and cloud features. Most significant was improved support for virtualization so developers can more flexibly assign SSD resources to specific virtual machines, thereby addressing latency.
Meanwhile, the eighth NVMe Plugfest at the University of New Hampshire Interoperability Laboratory last fall offered the first official NVMe Over Fabrics (NVMe-oF) compliance and interoperability transport layer testing for RoCE, Remote Direct Memory Access (RDMA) over Converged Ethernet, and the Fibre Channel. UNH-IOL fills the role of independent testing provider of standards conformance solutions and multi-vendor interoperability, and the latest plugfest generated 14 new certified products for the base NVMe integrators list and one for the NVMe-MI integrators list. Eight inaugural products were also approved for the newly launched NVMe-oF integrators list, which accepts RoCE initiators and targets, Ethernet switches, as well as Fibre Channel initiator, targets and switches and software.
Read the full story over at EE Times.
You’re probably all getting pretty tired of the debate raging on about the role of oil pipelines in our economy, but hopefully some info on clean tech has cut through all the noise. Behind the scenes, Canadian clean tech has been soldiering on, leveraging information technology, the Internet of Things (IoT), and even quantum computing to promote sustainability as modern tech drives us forward.
And with Canada’s Environment Minister as one of 30 committed to the Paris Accord, there are plenty of greenfield opportunities to build business solutions around clean tech in Canada. Better yet: There’s an important role for skilled IT people to play.
Read the full story over at HP Tektonika.
TORONTO — Last year could be described as a tipping point for the magneto-resistive random access memory (MRAM) market. Up until then, Everspin Technologies was the only company shipping commercial MRAM products. But as Spin Transfer Technologies (STT) CEO Barry Hoberman is always quick to acknowledge, Everspin’s success has helped to pave the way for other MRAM players.
The genesis of STT goes back as far as 2001 with technology originally developed from research conducted by New York University Professor Andrew Kent. STT was formed and incubated by Boston-based Allied Minds in 2007. In September 2016, the developer of orthogonal spin transfer MRAM technology (OST-MRAM) announced it had fabricated perpendicular MRAM magnetic tunnel junctions (MTJs) as small as 20nm at its development fab based at the company’s headquarters in Fremont, Calif.
Since then, STT has delivered samples of its spin transfer torque MRAM to customers in North America and Asia, a milestone that’s significant in that it’s one of several emerging memories considered to be a next-generation candidate to replace DRAM and NAND flash, which face scaling challenges as the industry moves to smaller nodes. STT is one of a handful of firms developing MRAM, so the delivery of samples is an important proof point validating both MRAM in general, and STT’s technology in particular.
EE Times recently spoke with Hoberman about the company’s ramp up, and the opportunities for MRAM as more players go to market, including where it might be a viable replacement for incumbent technologies.
Read the full Q&A on EE Times.
TORONTO – Statistically, flying is the safest way to travel. We don’t worry about airplanes dropping from the sky. But drones are another thing altogether.
If a drone runs into mechanical problems, there’s no Chesley “Sully” Sullenberger to land it on the Hudson River. To keep unmanned aerial vehicles (UAVs) from landing on our heads, NASA is trying to make them smarter.
Dubbed Safe2Ditch, the technology is aimed at allowing drones to continuously run self-diagnostics during flight to anticipate problems. If something goes wrong, the system could make changes to how the drone is flying and estimate how much longer it could stay in the air.
Since a drone with mechanical problems would need to set down quickly, Safe2Ditch would immediately begin to search its database for safe landing locations and autonomously land at the closest spot. Safe landing options would include fields, parking lots or parks, said Lou Glaab, assistant branch head for the Aeronautics Systems Engineering Branch at the NASA Langley Research Center. Worst case scenario, a drone might have to land in a dense forest to avoid people, but the goal is to keep avoid damaging the drone in an emergency landing.
Read my full article for EE Times.
TORONTO – As Ethernet speeds get faster, Rambus is looking to make sure memory and interfaces can keep up with the recent launch 56G SerDes PHY.
The analog-to-digital converter (ADC) and (DSP) architecture of the 56G SerDes PHY is designed meet the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications, said Mohit Gupta, senior director of product marketing at Rambus. This means it can support scaling to speeds as fast as 112G, which are required in the networking and enterprise segments, such as enterprise server racks that are moving from 100G to 400G.
“Ethernet is moving faster than ever,” Gupta said. “The pace has picked up substantially due to big data, the Internet of Things (IoT) and other trends putting high demands on communication channels. There is already a forum for 112G SerDes speed which will drive the 800G standard.”
One clear usage case, said Gupta, is data center deployment by the “big four” — Facebook, Microsoft, Amazon and Google.
Read my full article on EE Times.
Hosted data centers have become a common avenue for enterprises to access and deliver IT services, but they’re also a hit with cyber criminals.
According to a recent report by ThreatMatrix, there is a correlation between top U.S. cities for online fraud and those that are home to hosted data centers, with Tampa, Fla. topping the list, followed by New York. Major U.S. cities rounding out the top 10 included Los Angeles, Atlanta and Chicago. [Read the full story on IT World Canada]
The NVM Express Work Group has decided to incorporate itself to further the NVM Express (NVMe) specification for accessing solid-state disks (SSDs) on a PCI Express (PCIe) bus. NVMe is a standardized register interface, command, and feature set for PCIe-based storage technologies such as SSDs, designed specifically for non-volatile memory. It is optimized for high performance and low latency, scaling from client to enterprise segments. Read Full Article.
As DDR4 awaits widespread adoption and new technologies such as hybrid memory cube continue to be fleshed out, there remains opportunity to improve on DDR3’s performance, and more importantly, its design and manufacturing. Last week, Samsung announced it was mass producing what the company said is the most advanced 4Gb DDR3 memory based on a new 20 nanometer process technology using immersion ArF lithography. Read Full Article.
While businesses turn to proven systems for their high-performance computing needs, research institutions are more willing to experiment and take a chance on the latest and greatest to solve complex problems. The Japan Agency for Marine-Earth Science and Technology (JAMSTEC) is the perfect example: It recently selected SGI’s large-scale shared memory system, the UV 2000, for installation at its Earth Simulator supercomputer center. Read Full Article.